1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which performs refresh operations for retaining stored data.
2. Description of the Related Art
There is a strong demand for low power consumption with respect to semiconductor devices for use in portable equipment.
In DRAMs that store data in memory capacitors, refresh operations are constantly performed to retain information stored in the cells by successively activating word selecting lines to read cell data, amplifying the data potentials by use of sense amplifiers, and writing the amplified data back to the cells. Such refresh operations are performed even during a standby period, so that it is necessary to reduce the currents consumed during the refresh operations in order to suppress standby currents.
As a mechanism for reducing current consumption relating to refresh operations, provision may be made to provide a word line selecting shift register circuit corresponding one-to-one to each word line selecting decoder so as to select a word line selecting decoder based on the output of the word line selecting shift register circuit, rather than employing a configuration in which a counter circuit successively generates refresh addresses. With this provision, there is no need to charge and discharge the address signal lines laid out inside the semiconductor chip at the time of refresh operations, thereby making it possible to reduce the charging and discharging currents.
FIG. 1 is a diagram showing an example of the construction of a typical DRAM.
A DRAM 10 of FIG. 1 includes an address-&-command inputting unit 11, an I/O unit 12 for inputting/outputting data, cell array units 13-1 and 13-2, word decoder sets 14-1 and 14-2 for selecting word lines, amplifiers 15 for amplifying data signals when data is transmitted between the cell array units and the I/O unit, and Y decoders 16 for selecting data in the column direction. Each of the cell array units 13-1 and 13-2 is divided into a plurality of cell arrays 23. With respect to each of the cell arrays 23, a sense amplifier unit (S/A) 22 is provided to amplify a minute potential difference reflecting cell data on the bit lines, and a sub-word decoder (SWD) 21 is provided to selectively activate a word line.
In response to an entered address and command, a word line and a column line are selected, and a data read/write operation is performed with respect to a cell(s) positioned at the intersection of the selected word line and column line. In the case of write operation, data input into the I/O unit 12 is amplified by the amplifiers 15 and the sense amplifiers 22, followed by being stored in the selected cells. In the case of read operation, data read from the selected cells is amplified by the sense amplifiers 22 and the amplifiers 15, followed by being output to an exterior through the I/O unit 12.
In the case of refresh operations, a word line is selected according to an address for which refresh is required, and data is read from cells connected to the selected word line, Then, the data potentials are amplified by the sense amplifiers, followed by being stored back in the cells.
FIG. 2 is a drawing showing connections between word line selecting shift registers and word line selecting decoders provided for the purpose of refresh operations.
As shown in FIG. 2, one word line selecting shift register (S/R) 31 is provided for one word decoder 30 that corresponds to one main word line MWL. In the same manner as in FIG. 1, the left-side word decoder set 14-1 corresponds to the left-side cell array unit 13-1, and the right-side word decoder set 14-2 corresponds to the right-side cell array unit 13-2. Each word line selecting shift register 31 receives a control signal cntl. In response to each pulse of the control signal cntl, shift data such as “1” successively propagates from a given word line selecting shift register 31 to a next word line selecting shift register 31. A main word line MWL is selectively activated by the corresponding word decoder 30 where the corresponding word line selecting shift register 31 stores the shift data “1”.
Between the left-side word decoder set 14-1 and the right-side word decoder set 14-2, the shift data propagates through a signal line A so as to continue to propagate in the opposite direction.
In the related-art configuration shown in FIG. 2, no mechanism is provided to find which one of the word line selecting shift registers 31 is in the selected state. Accordingly, it is also unknown when the shift data of the word line selecting shift registers 31 propagates from the left-hand side to the right-hand side or from the right-hand side to the left-hand side, making it impossible to ascertain which one of the left-side cell array unit 13-1 and the right-side cell array unit 13-2 is currently subjected to refresh operations. Because of this, provision is made such that the control signal cntl is always supplied to both of the word decoder sets 14-1 and 14-2, rather than being selectively supplied to one of the word decoder sets 14-1 and 14-2. This results in unnecessary current consumption.
[Patent Document 1] Japanese Patent Application Publication No. 2000-311487